Line data    Source code

       1              : // *****************************************************************************
       2              : /*!
       3              :   \file      src/Inciter/kozcg.ci
       4              :   \copyright 2012-2015 J. Bakosi,
       5              :              2016-2018 Los Alamos National Security, LLC.,
       6              :              2019-2021 Triad National Security, LLC.,
       7              :              2022-2025 J. Bakosi
       8              :              All rights reserved. See the LICENSE file for details.
       9              :   \brief     Charm++ module interface for KozCG
      10              : */
      11              : // *****************************************************************************
      12              : 
      13              : module kozcg {
      14              : 
      15              :   extern module transporter;
      16              :   extern module discretization;
      17              : 
      18              :   include "UnsMesh.hpp";
      19              :   include "PUPUtil.hpp";
      20              : 
      21              :   namespace inciter {
      22              : 
      23              :     array [1D] KozCG {
      24              :       entry KozCG( const CProxy_Discretization& disc,
      25              :                    const std::map< int, std::vector< std::size_t > >& bface,
      26              :                    const std::map< int, std::vector< std::size_t > >& bnode,
      27              :                    const std::vector< std::size_t >& triinpoel );
      28              :       initnode void registerReducers();
      29              :       entry void setup( tk::real v );
      30              :       entry void start();
      31              :       entry void evalres( const std::vector< tk::real >& l2ref );
      32          459 :       entry [reductiontarget] void advance( tk::real newdt );
      33              :       entry void comnorm( const std::unordered_map< int,
      34         9006 :         std::unordered_map< std::size_t, std::array< tk::real, 4 > > >& inbnd );
      35              :       entry void comrhs( const std::unordered_map< std::size_t,
      36         4210 :                            std::vector< tk::real > >& inrhs );
      37              :       entry void comaec( const std::unordered_map< std::size_t,
      38         4210 :                            std::vector< tk::real > >& inaec );
      39              :       entry void comalw( const std::unordered_map< std::size_t,
      40         4210 :                            std::vector< tk::real > >& inalw );
      41              :       entry void comlim( const std::unordered_map< std::size_t,
      42         9006 :                            std::vector< tk::real > >& inlim );
      43              :       entry void feop();
      44              :       entry void step();
      45              :       entry void integrals();
      46              :       entry void evalLB( int nrestart );
      47              : 
      48              :       // SDAG code follows. See http://charm.cs.illinois.edu/manuals/html/
      49              :       // charm++/manual.html, Sec. "Structured Control Flow: Structured Dagger".
      50              : 
      51              :       entry void wait4int() {
      52              :         when ownnorm_complete(), comnorm_complete() serial { merge(); } }
      53              : 
      54              :       entry void wait4rhs() {
      55              :         when ownrhs_complete(), comrhs_complete() serial { fct(); } }
      56              : 
      57              :       entry void wait4aec() {
      58              :         when ownaec_complete(), comaec_complete() serial { alw(); } }
      59              : 
      60              :       entry void wait4alw() {
      61              :         when ownalw_complete(), comalw_complete() serial { lim(); } }
      62              : 
      63              :       entry void wait4sol() {
      64              :         when ownlim_complete(), comlim_complete() serial { solve(); } }
      65              : 
      66              :       entry void wait4step() {
      67              :         when feop_complete(), resize_complete() serial { out(); } }
      68              : 
      69              :       entry void ownnorm_complete();
      70              :       entry void comnorm_complete();
      71              :       entry void ownrhs_complete();
      72              :       entry void comrhs_complete();
      73              :       entry void ownaec_complete();
      74              :       entry void comaec_complete();
      75              :       entry void ownalw_complete();
      76              :       entry void comalw_complete();
      77              :       entry void ownlim_complete();
      78              :       entry void comlim_complete();
      79              :       entry void feop_complete();
      80              :       entry void resize_complete();
      81              :     }
      82              : 
      83              :   } // inciter::
      84              : 
      85              : }