Line data Source code
1 : // *****************************************************************************
2 : /*!
3 : \file src/Inciter/laxcg.ci
4 : \copyright 2012-2015 J. Bakosi,
5 : 2016-2018 Los Alamos National Security, LLC.,
6 : 2019-2021 Triad National Security, LLC.,
7 : 2022-2025 J. Bakosi
8 : All rights reserved. See the LICENSE file for details.
9 : \brief Charm++ module interface for LaxCG
10 : */
11 : // *****************************************************************************
12 :
13 : module laxcg {
14 :
15 : extern module transporter;
16 : extern module discretization;
17 :
18 : include "UnsMesh.hpp";
19 : include "PUPUtil.hpp";
20 :
21 : namespace inciter {
22 :
23 : array [1D] LaxCG {
24 : entry LaxCG( const CProxy_Discretization& disc,
25 : const std::map< int, std::vector< std::size_t > >& bface,
26 : const std::map< int, std::vector< std::size_t > >& bnode,
27 : const std::vector< std::size_t >& triinpoel );
28 : initnode void registerReducers();
29 321 : entry void setup( tk::real v );
30 : entry void start();
31 10350 : entry void evalres( const std::vector< tk::real >& l2ref );
32 : entry [reductiontarget] void advance( tk::real newdt );
33 10350 : entry void comnorm( const std::unordered_map< int,
34 : std::unordered_map< std::size_t, std::array< tk::real, 4 > > >& inbnd );
35 3450 : entry void comgrad( const std::unordered_map< std::size_t,
36 : std::vector< tk::real > >& ingrad );
37 : entry void comrhs( const std::unordered_map< std::size_t,
38 : std::vector< tk::real > >& inrhs );
39 : entry void feop();
40 : entry void step();
41 : entry void integrals();
42 : entry void stage();
43 : entry void evalLB( int nrestart );
44 :
45 : // SDAG code follows. See http://charm.cs.illinois.edu/manuals/html/
46 : // charm++/manual.html, Sec. "Structured Control Flow: Structured Dagger".
47 :
48 : entry void wait4int() {
49 : when ownnorm_complete(), comnorm_complete() serial { merge(); } }
50 :
51 : entry void wait4grad() {
52 : when owngrad_complete(), comgrad_complete() serial { rhs(); } }
53 :
54 : entry void wait4rhs() {
55 : when ownrhs_complete(), comrhs_complete() serial { solve(); } }
56 :
57 : entry void wait4stage() {
58 : when feop_complete(), resize_complete() serial { stage(); } }
59 :
60 : entry void ownnorm_complete();
61 : entry void comnorm_complete();
62 : entry void owngrad_complete();
63 : entry void comgrad_complete();
64 : entry void ownrhs_complete();
65 : entry void comrhs_complete();
66 : entry void feop_complete();
67 : entry void resize_complete();
68 : }
69 :
70 : } // inciter::
71 :
72 : }
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